The invention relates to semiconductor structures, and more particularly to three dimensional merged structures for implementing field effect transistor circuits.
Conventional MOS integrated circuits (often called "planar" devices) known in the prior art are characterized by the placement of the surfaces of the drain, source and channel active regions parallel to one of the flat major surfaces of the wafer or of the chip. The other flat major surface is usually used for mechanical fastening and electrical grounding of the chip to the package. Such device structures may be considered as "two dimensional" circuits, since no transistor device is placed perpendicular to the major surface which is subject to processing of MOS integrated circuit structure.
Vertical MOS (VMOS) structures known in the prior art adds the third dimension to the conventional MOS integrated circuits in that the plane defined by the surface of drain, source, and channel active regions forms an angle relative to the major surface of the wafer or of the chip utilized for processing, (i.e. a "V-groove" is formed on the major surface). The degree of the angle between the plane of the wafer and the plane formed by the MOS transistor surface depends upon the method of V-groove etching technology. Such devices may also be called "three dimensional" since the transistor structures utilize a penetration into the major silicon surface.
A vertical field effect transistor, such as described in U.S. Pat. No. 4,129,879, is also known which has a true "vertical" structure in which the current flow is essentially normal to the surface. Such a structure consists of a heavily doped semiconductor layer on which is formed a mesa structure including a moderately doped semiconductor layer and another heavily doped semiconductor layer, all of the layers being of the same conductivity type and with metallization on the external surfaces of the outer layers. Such a transistor is disclosed as having a Schottky gate junction on an insulated gate structure.
All of these prior art techniques provide individual devices, which must be interconnected by means of contacts and additional conducting materials like metal, polysilicon or highly doped semiconductor strips. More specifically constructing a gate or an amplifier or other circuit units. The output of the unit is always a highly doped semiconductor portion while the input is always a metal or polysilicon gate if transmission gates or grounded gate amplifiers are disregarded. The difference in material and in geometrical placement of the input and output requires at the minimum one contact to interconnect one device with another. A "contact" as used here means a direct mechanical surface-to-surface interface between metal or polysilicon and semiconductor. Such an interface is known to have a low, but not negligible, resistance, and a low potential barrier to the flow of mobile charge carriers. The contacts greatly enlarge the required silicon area for an MOS circuit, reduce reliability and operational speed.
Of less relevence, but which should be noted for completeness, are the merged bipolar transistor logic structures (also known as integrated injection logic or I.sup.2 L) which are known in the prior art, such as exemplified by U.S. Pat. No. 4,056,810, issued Nov. 1, 1977. Although such prior art discloses multi-layer current injectors and purports to suggest their applicability to a "field effect transistor" (column 7, lines 25-26), the full characterization of such transistors including their structure and mode of operation, is nowhere suggested.
The structure and operation of current injector devices and planar, vertical, or merged bipolar transistors are totally different from unipolar or field effect transistors, and the teaching of the bipolar art is not generally applicable to the field of the present invention.
Although both vertical bipolar devices and vertical MOS devices are known in the prior art, there is no teaching from such art on how vertical field effect transistors may be connected together in a circuit, or used together with planar MOS devices in a merged form, in which the drain or source region together with a gate region constitutes a contactless unit. Thus, prior to the present invention, although there have been various implementations of bipolar and field effect transistors as two dimensional devices, there has been no teaching on how such devices may be implemented in three dimensions, and more particularly how circuits of more than one device may be interconnected without additional semiconductor structures.